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| B9948L 2.5V/3.3V, 160-MHz, 1:12 Clock Distribution Buffer Product Features * * * * * * * * * * * 160-MHz clock support 2.5V or 3.3V output capability 200-ps maximum output-to-output skew LVPECL or LVCMOS/LVTTL clock input LVCMOS/LVTTL compatible inputs 12 clock outputs: drive up to 24 clock lines Synchronous Output Enable Output Three-state control Pin compatible with MPC948L Industrial temp. range: -40C to +85C 32-pin TQFP package Description The B9948L is a low-voltage clock distribution buffer with the capability to select either a differential LVPECL or a LVCMOS/ LVTTL compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL compatible. The twelve outputs are 2.5V or 3.3V LVCMOS or LVTTL compatible and can drive two series-terminated 50 transmission lines. With this capability the B9948L has an effective fanout of 1:24. The outputs can also be three-stated via the threestate input TS#. Low output-to-output skews make the B9948L an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. The B9948L also provides a synchronous output enable input for enabling or disabling the output clocks. Since this input is internally synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. Block Diagram Pin Configuration VSS Q0 VDDC Q1 VSS Q2 VDDC Q3 32 31 30 29 28 27 26 25 VDD PECL_CLK PECL_CLK# TCLK TCLK_SEL SYNC_OE TS# 0 1 VDDC 12 Q0-Q11 TCLK_SEL TCLK PECL_CLK PECL_CLK# SYNC_OE TS# VDD VSS 1 2 3 4 5 6 7 8 B9948L 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 VSS Q4 VDDC Q5 VSS Q6 VDDC Q7 Cypress Semiconductor Corporation Document #: 38-07080 Rev. *C * 3901 North First Street * San Jose Q11 VDDC Q10 VSS Q9 VDDC Q8 VSS * CA 95134 * 408-943-2600 Revised December 21, 2002 B9948L Pin Description[1] Pin 3 4 2 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 1 5 Name PECL_CLK PECL_CLK# TCLK Q(11:0) VDDC PWR I/O I, PU I, PD I, PU O PECL Input Clock. PECL Input Clock. External Reference/Test Clock Input. Clock Outputs. Description TCLK_SEL SYNC_OE I, PU I, PU Clock Select Input. When LOW, PECL clock is selected and when HIGH TCLK is selected. Output Enable Input. When asserted HIGH, the outputs are enabled and when set low the outputs are disabled in a LOW state. Three-state Control Input. When asserted LOW, the output buffers are three-stated. When set HIGH, the output buffers are enabled. 2.5V or 3.3V Power Supply for Output Clock Buffers. 3.3V Power Supply. Common Ground. 6 TS# I, PU 10, 14, 18, 22, 26, 30 7 8, 12, 16, 20, 24, 28, 32 VDDC VDD VSS Note: 1. PD = Internal Pull-Down, PU = Internal Pull-Up. Output Enable/Disable The B9948L features a control input to enable or disable the outputs. This data is latched on the falling edge of the input clock. When SYNC_OE is asserted LOW, the outputs are disabled in a LOW state. When SYNC_OE is set HIGH, the outputs are enabled as shown in Figure 1. TCLK SYNC_OE Q Figure 1. SYNC_OE Timing Diagram Document #: 38-07080 Rev. *C Page 2 of 6 B9948L Maximum Ratings[2] Maximum Input Voltage Relative to VSS: ............ VSS - 0.3V Maximum Input Voltage Relative to VDD:............. VDD + 0.3V Storage Temperature: ................................-65C to + 150C Operating Temperature: ................................ -40C to +85C Maximum ESD protection ............................................... 2 kV Maximum Power Supply: ................................................5.5V Maximum Input Current:..................................................20 mA This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Parameters: VDDC = 2.5V5% or 3.3V 5%, VDD = 3.3V 5%, TA = -40C to +85C Parameter VIL VIH IIL IIH VPP VCMR VOL VOH IDD Cin Description Input Low Voltage Conditions PECL_CLK, Single ended All other inputs Input High Voltage PECL_CLK, Single ended All other inputs Input Low Current (@VIL = VSS) Input High Current (@VIL =VDD) Peak-to-Peak Input Voltage PECL_CLK Common Mode Range PECL_CLK Output Low Voltage Output High Voltage IOL = 20 mA [5] [5] [5] Min. 1.49 VSS 2.135 2.0 Typ. Max. 1.825 0.8 2.42 VDD -100 100 Unit V V Note 3 A A mV V V V Note 4 300 VDD - 2.0 1000 VDD - 0.6 0.4 IOH = -20 mA, VDDC = 3.3V IOH = -20 mA, VDDC = 2.5V All VDDC and VDD 2.5 2.0 1 2 4 Quiescent Supply Current Input Capacitance mA pF Notes: 2. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Inputs have pull-up resistors that effect input current, PECL_CLK# has a pull-down resistor. 4. 5. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the "High" input is within the VCMR range and the input lies within the VPP specification. Driving series or parallel terminated 50 (or 50 to VDD/2) transmission lines. Document #: 38-07080 Rev. *C Page 3 of 6 B9948L AC Parameters[6]: VDDC = 2.5V5% or 3.3V 5%, VDD = 3.3V 5%, TA = -40C to +85C Parameter Fmax Tpd Description Maximum Input Frequency[7] PECL_CLK to Q Delay[7] TCLK to Q Delay[7] FoutDC tpZL, tpZH tpLZ, tpHZ Tskew Tskew (pp) Output Duty Cycle[7,8] Output enable time (all outputs) Output disable time (all outputs) Output-to-Output Skew Part to Part Skew[10] [7,11] [7,9] Conditions Min. 160 4.0 4.4 Typ. Max. Unit MHz - 9.0 8.9 TCYCLE/2 + 1000 10 10 200 ns Measured at VDDC/2 TCYCLE/2 - 1000 2 2 ps ns ns ps ns PECL_CLK to Q TCLK to Q 1.5 2.0 1.0 0.0 0.0 1.0 0.3 1.6 Ts Set-up Time SYNC_OE to PECL_CLK SYNC_OE to TCLK ns Th Hold Time[7,11] [9] PECL_CLK to SYNC_OE TCLK to SYNC_OE ns Tr/Tf Output Clocks Rise/Fall Time 10% to 90% ns Notes: 6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 7. Outputs driving 50 transmission lines. 8. 50% input duty cycle. 9. Outputs loaded with 30 pF each 10. Part-to-Part Skew at a given temperature and voltage. 11. Set-up and Hold times are relative to the falling edge of the input clock Ordering Information Part Number[12] B9948LAA Package Type 32-Pin TQFP Industrial, -40C to +85C Production Flow Note: 12. The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: Cypress B9948LAA Date Code, Lot # B9948LAA Package A = TQFP Revision Device Number Document #: 38-07080 Rev. *C Page 4 of 6 B9948L Package Drawing and Dimensions 32-Pin TQFP Outline Dimensions Inches Symbol D Ml Max. 0.047 0.006 0.041 0.018 Min. 0.05 0.95 0.30 Nom. 9.00 7.00 0.80 BSC 0.030 0.45 0.75 Max. 1.20 0.15 1.05 0.45 Min. 0.002 0.037 0.012 Nom. 0.354 0.276 0.031 BSC A A1 A2 D D1 D1 12 A1 b e L 0.018 - L e b Document #: 38-07080 Rev. *C Page 5 of 6 (c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. B9948L Document Title: B9948L 2.5V/3.3V, 160 MHz, 1:12 Clock Distribution Buffer Document Number: 38-07080 Rev. ** *A *B *C ECN No. 107116 108061 109806 122765 Issue Date 06/06/01 07/03/01 02/01/02 12/21/02 Orig. of Change IKA NDP DSG RBI Description of Change Convert from IMI to Cypress Changed Commercial to Industrial (See page 6) Convert from Word to Frame Add power up requirements to maximum ratings information. Document #: 38-07080 Rev. *C Page 6 of 6 |
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